Combined nanoscale and device-level degradation analysis of SiO2 layers of MOS nonvolatile memory devices

Mario Lanza, Marc Porti, Montserrat Nafría, Xavier Aymerich, Alessandro Sebastiani, Gabriella Ghidini, Anna Vedda, M. Fasoli

Research output: Chapter in Book/Report/Conference proceedingConference contribution

11 Scopus citations

Abstract

In this paper, the impact of an electrical stress applied on MOS structures with a 9.8-nm-thick SiO2 layer has been investigated at the device level and at the nanoscale with conductive atomic force microscopy (AFM). The goal is to correlate both kinds of measurements when studying the degradation and breakdown (BD) of tunnel oxides of nonvolatile memory devices. In particular, the generation of defects and its impact on leakage current and charge trapping in the tunnel oxide have been analyzed through spectroscopic measurements and current images. The properties and energy of the stress-induced defects (before and after BD) have been roughly estimated by thermally stimulated luminescence and AFM measurements. © 2009 IEEE.
Original languageEnglish (US)
Title of host publicationIEEE Transactions on Device and Materials Reliability
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages529-536
Number of pages8
DOIs
StatePublished - Jan 1 2009
Externally publishedYes

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering
  • Safety, Risk, Reliability and Quality

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