Characterizing Latency Overheads in the Deployment of FPGA Accelerators

Ryan A. Cooke, Suhaib A. Fahmy

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

FPGA hardware accelerators have recently enjoyed significant attention as platforms for further accelerating computation in the datacenter but they potentially add additional layers of hardware and software interfacing that can further increase communication latency. In this paper, we characterize these overheads for streaming applications where latency can be an important consideration. We examine the latency and throughput characteristics of traditional server-based PCIe connected accelerators, and the more recent approach of network attached FPGA accelerators. We additionally quantify the additional overhead introduced by virtualising accelerators on FPGAs.
Original languageEnglish (US)
Title of host publicationProceedings - 30th International Conference on Field-Programmable Logic and Applications, FPL 2020
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages347-352
Number of pages6
ISBN (Print)9781728199023
DOIs
StatePublished - Aug 1 2020
Externally publishedYes

Fingerprint Dive into the research topics of 'Characterizing Latency Overheads in the Deployment of FPGA Accelerators'. Together they form a unique fingerprint.

Cite this