Adaptive systems have the ability to respond to environmental conditions by modifying their processing at runtime. This can be implemented by using partial reconfiguration (PR) on FPGAs. However, designing such systems requires specialist architecture knowledge and an understanding of the mechanics of reconfiguration, as the design process is completely manual. One design choice that must be made, which impacts system efficiency significantly, is how to group reconfigurable modules and assign them to reconfigurable regions on the FPGA. In this paper, we present an approach, based on graph clustering, that finds a partitioning that minimises reconfiguration time, given an application description and target FPGA. The resulting allocation respects all the constraints set by the official tool flow while raising the level of design abstraction, allowing non-expert designers to leverage this capability of FPGAs. © 2013 IEEE.
|Original language||English (US)|
|Title of host publication||Proceedings - IEEE 27th International Parallel and Distributed Processing Symposium Workshops and PhD Forum, IPDPSW 2013|
|Publisher||IEEE Computer Societyhelp@computer.org|
|Number of pages||10|
|State||Published - Jan 1 2013|