Analysis and demonstration of MEM-relay power gating

Hossein Fariborzi*, Matthew Spencer, Vaibhav Karkare, Jaeseok Jeon, Rhesa Nathanael, Chengcheng Wang, Fred Chen, Hei Kam, Vincent Pott, Tsu Jae King Liu, Elad Alon, Vladimir Stojanović, Dejan Marković

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

24 Scopus citations

Abstract

This paper shows that due to their negligibly low leakage, in certain applications, chips utilizing power gates built even with today's relatively large, high-voltage micro-electro-mechanical (MEM) relays can achieve lower total energy than those built with CMOS transistors. A simple analysis provides design guidelines for off-time and savings estimates as a function of technology parameters, and quantifies the further benefits of scaled relay designs. Finally, we demonstrate a relay chip successfully power-gating a CMOS chip, and show a relay-based timer suitable for self-timed operation.

Original languageEnglish (US)
Title of host publicationIEEE Custom Integrated Circuits Conference 2010, CICC 2010
DOIs
StatePublished - Dec 13 2010
Event32nd Annual Custom Integrated Circuits Conference - The Showcase for Circuit Design in the Heart of Silicon Valley, CICC 2010 - San Jose, CA, United States
Duration: Sep 19 2010Sep 22 2010

Publication series

NameProceedings of the Custom Integrated Circuits Conference
ISSN (Print)0886-5930

Other

Other32nd Annual Custom Integrated Circuits Conference - The Showcase for Circuit Design in the Heart of Silicon Valley, CICC 2010
CountryUnited States
CitySan Jose, CA
Period09/19/1009/22/10

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Fingerprint

Dive into the research topics of 'Analysis and demonstration of MEM-relay power gating'. Together they form a unique fingerprint.

Cite this