An enhanced 90nm high performance technology with strong performance improvements from stress and mobility increase through simple process changes

R. Khamankar*, H. Bu, C. Bowen, S. Chakravarthi, P. R. Chidambaram, M. Bevan, A. Krishnan, H. Niimi, B. Smith, J. Blatchford, B. Hornung, J. P. Lu, P. Nicollian, B. Kirkpatrick, D. Miles, M. Hewson, D. Farber, L. Hall, Husam Niman Alshareef, A. VargheseA. Gurba, V. Ukraintsev, B. Rathsack, J. DeLoach, J. Tran, C. Kaneshige, M. Somervell, S. Aur, C. Machala, T. Grider

*Corresponding author for this work

Research output: Contribution to journalConference articlepeer-review

20 Scopus citations

Abstract

In this abstract we present a highly manufacturable, high performance 90nm technology with best in class performance for 35nm gate-length N and P transistors. Unique, but simple and low cost, process changes have been utilized to modulate channel stress and implant profile to generate enhanced performance with no additional masks. High drive currents of 1193uA/um and 587uA/um are obtained for nMOS and pMOS transistors respectively at 1.2V Vdd and an Ioff of 60nA/μm. An industry leading 90nm technology CV/I of 0.61ps and 1.12ps are obtained for nMOS and pMOS transistors respectively. An aggressively scaled 12Å EOT plasma-nitrided, cluster gate dielectric is used. Process conditions are optimized to obtain high drive current, good Vt roll-off control and simultaneously meet reliability requirements.

Original languageEnglish (US)
Pages (from-to)162-163
Number of pages2
JournalDigest of Technical Papers - Symposium on VLSI Technology
StatePublished - Oct 1 2004
Event2004 Symposium on VLSI Technology - Digest of Technical Papers - Honolulu, HI, United States
Duration: Jun 15 2004Jun 17 2004

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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