Alternative approaches for high-k/metal gate CMOS: Low temperature process (gate last) and SiGe channel

C. S. Park, Muhammad Mustafa Hussain, K. Tateiw, J. Huang, J. Lin, T. Ngai, S. Lian, K. Rader, B. Taylor, P. D. Kirsch, R. Jammy

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

7 Scopus citations

Abstract

A comprehensive materials set has been fabricated and characterized to address the challenging issues in both gate first and gate last HK/MG CMOS. Specifically, metal gate thermal budget and channel composition are shown to be effective methods to engineer pMetal effective work function for gate last and gate first, respectively. Low temperature processing has resulted in low nMOS Vfb and high pMOS Vfb (ΔEWF=∼900mV) without the Vfb roll-off typically observed for gate first pMetals. Gate first high-k/metal gate CMOS has also been demonstrated using dual channel, single metal gate. Excellent pFET Ion-Ioff characteristics, 500 μA/μm at 1nA/μm for Vdd=1V have been achieved without additional strain engineering owing to: [i] optimized SiGe thickness, [ii] optimized Ge concentration, [iii] reduced Rext,[iv] minimized Coulomb scattering at short channel, and [v] scaled gate oxide thickness.

Original languageEnglish (US)
Title of host publicationProceedings of 2010 International Symposium on VLSI Technology, System and Application, VLSI-TSA 2010
Pages80-81
Number of pages2
DOIs
StatePublished - Oct 20 2010
Event2010 International Symposium on VLSI Technology, System and Application, VLSI-TSA 2010 - Hsin Chu, Taiwan, Province of China
Duration: Apr 26 2010Apr 28 2010

Publication series

NameProceedings of 2010 International Symposium on VLSI Technology, System and Application, VLSI-TSA 2010

Other

Other2010 International Symposium on VLSI Technology, System and Application, VLSI-TSA 2010
CountryTaiwan, Province of China
CityHsin Chu
Period04/26/1004/28/10

ASJC Scopus subject areas

  • Computer Networks and Communications
  • Hardware and Architecture

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