Computing based on traditional approaches has hit its limits in terms of scalability and power consumption. For this reason, new computing paradigms have started to emerge that aim to perform operations directly in-memory to eliminate data movement costs. Even though traditional in-memory processor architectures together with emerging semiconductor technologies show promise for improving the efficiency of parallel computing, they lack some vital requirements such as flexibility and sequential execution. In this paper, a novel 2-D in-memory computing architecture is proposed. The proposed associative processing architecture is implemented by both CMOS/static random-access memory and ReRAM technologies and employed as an accelerator. As proven by circuit simulations and comparisons on a variety of benchmarks from different domains, the proposed architecture facilitates very efficient in-memory parallel computing together with a high degree of flexibility that results in faster running time in fundamental benchmarks.
|Original language||English (US)|
|Journal||IEEE Transactions on Very Large Scale Integration (VLSI) Systems|
|State||Published - Sep 1 2018|