In this paper, a novel technique for enhancement of hysteresis comparators is proposed. This work is based on an improved version of hysteresis comparators that used NMOS current mirrors, a PMOS load stage and a PMOS tail transistor to reduce the static power. By using an internal biasing technique for the tail transistor, we eliminated the need for one of the biasing circuits while achieving 65% lower power consumption in 0.18μ m CMOS technology, without much impact on the trip values of the hysteresis comparator.
|Original language||English (US)|
|Title of host publication||2018 25th IEEE International Conference on Electronics, Circuits and Systems (ICECS)|
|Publisher||Institute of Electrical and Electronics Engineers (IEEE)|
|Number of pages||4|
|State||Published - Jan 24 2019|