This paper addresses the issue of designing scalable prototypes for multi input multi output (MIMO) wireless channel emulation. To date, emulators are extending single input single output (SISO) time based Altering techniques to emulate MIMO channels, which in turn requires quadratic increase in computational resources as the array size increases. In this paper, a new scalable approach for MIMO wireless channel emulation is presented. It is shown that for a 2×2 MIMO system, by performing channel emulation in the frequency domain, a reduction of up to 43 % in computations per output sample can be achieved as compared to traditional techniques. For higher order arrays, further reduction is possible. It is also illustrated that a linear growth in computational resources is attained through this scheme. The architecture is presented and synthesis results using an FPGA platform are discussed.
|Original language||English (US)|
|Title of host publication||IEEE International Conference on Communications|
|State||Published - Dec 1 2007|