A scalable and highly manufacturable single metal gate/high-k CMOS integration for sub-32nm technology for LSTP applications

C. S. Park, Muhammad Mustafa Hussain, J. Huang, C. Park, K. Tateiwa*, C. Young, H. K. Park, M. Cruz, D. Gilmer, K. Rader, J. Price, P. Lysaght, D. Heh, G. Bersuker, P. D. Kirsch, H. H. Tseng, R. Jammy

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

11 Scopus citations

Abstract

This paper reports on a scalable and simple gate-first integration option for manufacturing the high-k/metal gate CMOS transistors targeting sub-32nm LSTP applications: V t <±0.45V (at L g =60nm) at EOT≤1.4nm, with 10 5 × J g reduction compared to SiO 2 . This scheme integrates several simplifications and improvements for the first time: single metal gate material, single channel material, dual selective LaO x / AlO x cap removal without lithographic overlay tolerances issues and optimized HfSiON for LSTP leakage targets.

Original languageEnglish (US)
Title of host publication2009 Symposium on VLSI Technology, VLSIT 2009
Pages208-209
Number of pages2
StatePublished - Nov 16 2009
Externally publishedYes
Event2009 Symposium on VLSI Technology, VLSIT 2009 - Kyoto, Japan
Duration: Jun 16 2009Jun 18 2009

Publication series

NameDigest of Technical Papers - Symposium on VLSI Technology
ISSN (Print)0743-1562

Other

Other2009 Symposium on VLSI Technology, VLSIT 2009
CountryJapan
CityKyoto
Period06/16/0906/18/09

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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