This paper introduces a low-power time-domain comparator with a modified current starved inverter circuit. The proposed comparator converts the analog input voltage into a time delay that creates a phase difference between the input signal and the reference signal. Then a phase detector is utilized to determine either the input signal is leading or lagging compared to the reference signal. Moreover, the power optimization is achieved by limiting the short circuit power (PSC) that passes through both charging and discharging phases. A prototype of the proposed comparator is designed and simulated in 0.13 µm CMOS technology where it draws 0.6 µA from a 1 V supply with a sampling rate equals 10 MHz. Moreover, the simulation results of the proposed comparator offer a FoM of 60 fJ/conversion step. Finally, the proposed time-domain comparator circuit is compatible with wide range of applications (i.e., internet of things (IoT) sensors and integrated DC-DC converters).
|Original language||English (US)|
|Title of host publication||2018 IEEE 61st International Midwest Symposium on Circuits and Systems (MWSCAS)|
|Publisher||Institute of Electrical and Electronics Engineers (IEEE)|
|Number of pages||4|
|State||Published - Feb 28 2019|