In this paper, an idea for a new frequency divider architecture is proposed. The divider is based on a coarse-fine architecture. The coarse block operates at a low frequency to save power consumption and it selectively enables the fine block which operates at the high input frequency. The proposed divider has the advantages of synchronous divider, but with lower power consumption and higher operation speed. The design can achieve a wide division range with a minor effect on power consumption and speed. The architecture was implemented on a complex programmable logic device (CPLD) to verify its operation. Experimental measurements validate system operation with power reduction greater than 40%. © 2011 IEEE.
|Original language||English (US)|
|Title of host publication||2011 IEEE 54th International Midwest Symposium on Circuits and Systems (MWSCAS)|
|Publisher||Institute of Electrical and Electronics Engineers (IEEE)|
|State||Published - Aug 2011|