In this paper, a new design has been proposed for a high speed, low power StrongARM latch in 65nm CMOS technology. Latching speed improvements of 18% and 16% have been achieved in comparison to the conventional  and improved StrongARM , respectively, while the energy consumption has also been reduced.
|Original language||English (US)|
|Title of host publication||2018 IEEE 61st International Midwest Symposium on Circuits and Systems (MWSCAS)|
|Publisher||Institute of Electrical and Electronics Engineers (IEEE)|
|Number of pages||2|
|State||Published - Feb 28 2019|