A High Performance 90 nm Logic Technology with a 37nm Gate Length, Dual Plasma Nitrided Gate Dielectric and Differential Offset Spacer

B. Hornung*, R. Khamankar, H. Niimi, M. Goodwin, L. Robertson, D. Miles, B. Kirkpatrick, Husam Niman Alshareef, A. Varghese, M. Bevan, P. Nicollian, P. R. Chidambaram, S. Chakravarthi, A. Gurba, X. Zhang, J. Blatchford, B. Smith, J. P. Lu, J. Deloach, B. RathsackC. Bowen, G. Thakar, C. Machala, T. Grider

*Corresponding author for this work

Research output: Contribution to journalConference articlepeer-review

6 Scopus citations

Abstract

A 90nm logic technology is presented featuring an aggressively scaled 37nm gate length, 1.3 nm EOT plasma nitrided gate dielectric with differential offset spacer and leading edge CV/I performance. NMOS and PMOS transistors have been optimized with different extension offsets for NMDD and PMDD implants, which enables independent optimization of short channel effects, parasitic capacitance and drive current. The gate dielectric meets reliability requirements at 1.2V operation. The technology includes a standard Vt (SVt) transistor, low Vt (LVt) transistor and 1.5V IO transistor with lOOnm gate length and dual plasma nitrided gate dielectric.

Original languageEnglish (US)
Pages (from-to)85-86
Number of pages2
JournalDigest of Technical Papers - Symposium on VLSI Technology
StatePublished - Oct 1 2003
Event2003 Symposium on VLSI Technology - Kyoto, Japan
Duration: Jun 10 2003Jun 12 2003

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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