This letter presents the smallest reported 5 GHz receiver chip (1.3 mm 2) with an on-chip antenna in standard 0.13 μm CMOS process. The miniaturization is achieved by placing the circuits inside a meandered antenna. The on-chip antenna is conjugately matched to the low noise amplifier (LNA) over a wide frequency range. The design methodology for co-design of the on-chip antenna and LNA is described. The LNA is completely differential, consumes only 8 mW of power and provides a gain of 21 dB. Design tradeoffs and measurement challenges are given.
- Low noise amplifier (LNA)
- On-chip antenna
ASJC Scopus subject areas
- Condensed Matter Physics
- Electrical and Electronic Engineering