Recent power reduction techniques aggressively modulate the supply voltage of embedded buffering memories allowing acceptable hardware errors to flow through the processing chain. In this paper, we introduce a class of modified Turbo and LDPC decoders that provide significant improvements over standard decoders in the presence of hardware noise. Simulation results show a consistent improvement in the BER performance of the modified decoders across all SNRs with very small area and power overheads as compared to the conventional decoders. © 2011 IEEE.
|Original language||English (US)|
|Title of host publication||GLOBECOM - IEEE Global Telecommunications Conference|
|State||Published - Dec 1 2011|