This work proposes an efficient 4-bit flash ADC based on the StrongARM comparator architecture. The proposed design eliminates the need for the resistive ladder by systematically modifying the sizing of the input differential pair of each comparator. As a consequence, the area and the power consumed within the ladder is eliminated. Furthermore, a Helpee StrongARM circuit is introduced which enables operation at an input voltage below the threshold voltage of the transistor. An enhanced 1-out-of-15 decoder converts the thermometer code from the StrongARM and the Helpee StrongARM comparators into a 1-out-of-n code. The proposed 4-bit flash ADC architecture, simulated in 90nm standard CMOS technology, consumes 292 μ W at 1.6 GHz sampling frequency, has an ENOB of 3.88 and FoM of 12.4 fJ/conv.step.
|Original language||English (US)|
|Title of host publication||2018 14th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME)|
|Publisher||Institute of Electrical and Electronics Engineers (IEEE)|
|Number of pages||4|
|State||Published - Aug 17 2018|