65NM yield detractor caused by M1 filament shorts and solution

Y. C. Ee, S. K. Tan, C. S. Chee, J. B. Tan, B. C. Zhang, Y. K. Siew, P. K. Tan, F. Zhang, K. H. Lai, M. S. Chettiar, Xianbin Wang, Thomas Fu, L. C. Hsia, A. Inani, N. Akiya, L. Yuan, A. Agarwal

    Research output: Contribution to conferencePaperpeer-review

    Abstract

    Device scaling has been implemented throughout the chip making industry as a means of increasing density and performance. This has imposed a lot of challenging tasks to develop new processes, improve process window and reduce defect density. In our fabrication of 65nm W contact to Ml scheme, we found severe metal 1 shorts after electrical testing, these shorts potentially causing drop in SRAM yield of ∼ 40%. It is interesting to note that Ml shorts are induced by W CMP process. Detailed investigation showed that Ml shorts are related to post-W CMP topography and high-density of contact, which trap W-residues. This has subsequently affected Ml patterning processes. Electrical testing result shows the dependency of Ml failure rate on contact pattern density. In addition, cross-section TEM micrograph shows that adjacent metal lines are connected by filament, which contained Cu by EDX measurement. Base on our hypothesis, we have proposed the best ways to suppress this issue by optimizing W CMP platen 3 polishing time and DI water buffing time.

    Original languageEnglish (US)
    Pages117-122
    Number of pages6
    StatePublished - Dec 1 2007
    Event12th International Chemical-Mechanical Planarization for ULSI Multilevel Interconnection Conference, CMP-MIC 2007 - Fremont, CA, United States
    Duration: Mar 6 2007Mar 8 2007

    Other

    Other12th International Chemical-Mechanical Planarization for ULSI Multilevel Interconnection Conference, CMP-MIC 2007
    CountryUnited States
    CityFremont, CA
    Period03/6/0703/8/07

    Keywords

    • Ml shorts and Contact Pattern Density
    • W CMP

    ASJC Scopus subject areas

    • Hardware and Architecture
    • Electrical and Electronic Engineering

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