3D Monolithic Stacked 1T1R cells using Monolayer MoS 2 FET and hBN RRAM Fabricated at Low (150°C) Temperature

Ching Hua Wang, Connor McClellan, Yuanyuan Shi, Xin Zheng, Victoria Chen, Mario Lanza, Eric Pop, H. S. Philip Wong

Research output: Chapter in Book/Report/Conference proceedingConference contribution

6 Scopus citations

Abstract

We demonstrate 3D monolithically integrated two-level stacked 1-transistor/1-resistor (1T1R) memory cells, using monolayer MoS 2 transistors and few-layer hBN RRAMs, fabricated at temperatures below 150 °C. The stacking process is scalable to an arbitrarily large number of layers and on any substrate material without foreseeable physical limitations. The 1T1R cells can be switched with programming current < 130 μA and voltage < 1 V, close to typical CMOS logic voltages. These cells are promising for in-memory and neuromorphic computing because (1) the hBN RRAM has gradual set and reset switching due to multiple weak-filaments formed along local defects and (2) the MoS 2 transistor has low off-current due to the large band gap of monolayer MoS 2 (E g > 2 eV). We also show that the linearity of RRAM resistance change is well-controlled by the gate voltage of the transistor.
Original languageEnglish (US)
Title of host publicationTechnical Digest - International Electron Devices Meeting, IEDM
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages22.5.1-22.5.4
Number of pages1
ISBN (Print)9781728119878
DOIs
StatePublished - Jan 16 2019
Externally publishedYes

Fingerprint Dive into the research topics of '3D Monolithic Stacked 1T1R cells using Monolayer MoS 2 FET and hBN RRAM Fabricated at Low (150°C) Temperature'. Together they form a unique fingerprint.

Cite this